In many applications, data must be buffered in a pipeline register. For example, when the data to be processed in a single clock cycle exceeds the available processing capacity, the data can be stored in a pipeline register between clock cycles. FIG. 1 is a schematic block diagram illustrating a conventional pipeline architecture 100. As shown in FIG. 1, a pipelined register 100 typically comprises a plurality of hardware stages 110-1 through 110-N (N is equal to 4 in the exemplary embodiment). The hardware stages 110 are each embodied as memory registers, such as flip flops in the exemplary embodiment, connected in series.
The flip flops 110 store a sequence of data bits that ate passed from one flip flop 110-i to the next flip flop 110-i+1 in the series on each clock cycle (CLK). The same clock signal, CLK, is applied to the clock input of each flip flop 110 in the pipeline buffer 100 by means of a known clock tree 120. The enable input of each flip flop 110 is connected to the same enable port, EN, of the pipeline buffer 100. The data bits are sequentially transferred from one flip flop 110-i to a subsequent flip flop 110-i+1 in the pipeline 100 and each flip flop 110 is loaded with the next data bit in line. Since the flip flops 10 operate substantially concurrently, a pipelined system can operate faster than a non-pipelined system.
It has been found that the hold time constraints of a pipeline buffer 100 can be difficult to manage at high frequencies. In particular, the hold time constraint requires that the clock signal must arrive to the flip flop faster than the data arrives through the previous flip flop in the chain. The hold time constraint may not be guaranteed due to clock uncertainty for the longest clock tree paths. A need therefore exists for a pipeline architecture that can satisfy the flip flop hold time constraints for higher frequencies.